The integration of high value capacitors in integrated circuits is limited by the fact that conventional high value capacitors take up a large areas of on integrated circuit chip, and severely restrict interconnect routing in the region of the capacitor, thus reducing the device packing density and layout efficiency. Many applications, including telecommunications equipment, require a large number of capacitors, e.g. as coupling/decoupling capacitors and for filters. Often, these must be incorporated as discrete off-chip components, substantially increasing the bulk of the peripheral circuitry. In view of increasing demand for compact lightweight portable electronic equipment, e.g. wireless phones, it is desirable that the number of discrete components are reduced.
The minimum dimensions of integrated circuit capacitors are determined primarily by the relatively low dielectric constant (e&lt;10), of conventional capacitor dielectrics, e.g. silicon dioxide and silicon nitride. Thus as device dimensions decrease, there is increasing interest in other dielectrics with higher dielectric constants, e.g. tantalum oxide, and more particularly, ferroelectric dielectrics, which have very high dielectric constants (e&gt;&gt;100).
During the last few years, the use of the ferroelectric materials for random access memory (RAM) elements has reached commercial applications in the semiconductor industry. Ferroelectric dielectrics provide for formation of non volatile memories, with advantages including low voltage programmability, fast access times, and low power consumption.
The ferroelectric dielectric materials which have allowed this breakthrough in integrated circuit applications include perovskite structure ferroelectric dielectric compounds, for example, lead zirconate titanate PbZr.sub.x Ti.sub.1-x O.sub.3 (PZT), barium titanate (BT), and barium strontium titanate (BST).
These ferroelectric materials have large dielectric constants (.about.500), and thus they are also ideally suited as dielectrics for fabrication of integrated circuit capacitors with small dimensions and large capacitance values, e.g. for use as coupling/de-coupling capacitors and as filter elements.
Nevertheless several challenges and concerns have to be addressed in the integration of ferroelectric materials with monolithic integrated circuits. These challenges include the selection of suitable materials for bottom and top electrodes, and for barrier layers and capping layers, to avoid or control contamination problems. Because ferroelectric materials contain chemical elements not typically found in conventional integrated circuit materials, interdiffusion of elements of the ferroelectric material, heavy metals from the electrode materials, and surrounding materials may occur, causing contamination and degradation of electrical characteristics. This is of particular concern where ferroelectric materials are in close proximity to active devices.
Known methods of forming ferroelectric materials require relatively high temperature heat treatment to form a crystalline ferroelectric phase. The relatively high crystallization temperature limits the application of ferroelectric materials in back-end processing (i.e. during steps such as formation of interconnect and contact metallization) which require a relatively low thermal budget. For example, a layer of a ferroelectric precursor material is deposited in an amorphous form, by a known sol-gel process, followed by annealing, typically above 650.degree. C., to transform the amorphous, as-deposited layer into a crystalline phase, i.e. a perovskite ferroelectric dielectric phase, which has the required ferroelectric dielectric characteristics, characteristic functional properties. Thus, if the interconnect metallization comprises an Al alloy (melting point .about.600.degree. C.) or other material which cannot tolerate a large thermal budget (i.e. high temperature and or extended time at elevated temperature), all higher temperature process steps, including deposition and annealing of the ferroelectric layers must be completed before forming the metallization.
For these reasons, ferroelectric capacitors are typically incorporated into the usual process flow after completion of the active devices and before forming the interconnect metallization.
For example, after fabrication of the active devices, a conventional capacitor structure is often formed on a field isolation layer. When ferroelectric capacitors are to be fabricated, a suitable barrier layer is deposited overall to protect underlying structures from diffusion and contamination. A first layer of conductive material is deposited on the surface to form the bottom electrode. For a ferroelectric capacitor, the bottom electrode may be a single layer of conductive material, typically platinum, or preferably a multilayer stack, including an appropriate adhesion layer and/or barrier layer. A layer of ferroelectric dielectric material, e.g. PZT or BST, is deposited over the bottom electrode, and a second conductive layer is then deposited on the dielectric to form the top electrode. Again the top electrode may be a multilayer stack. The layers forming the electrodes and dielectric may be patterned together in a single stack to define the capacitor structure. Alternatively, the layers may be individually deposited and patterned to define sequentially the bottom electrode, the capacitor dielectric and the top electrode. After the ferroelectric capacitor structure is formed, a capping layer is deposited overall to encapsulate the capacitor structure. The capping layer is necessary to form another diffusion barrier, to prevent out-diffusion of the ferroelectric material and heavy metal electrode materials into the surrounding regions. The capping layer also prevents in-diffusion of unwanted species which are used in the latter stages of semiconductor processing, which may be detrimental to the ferroelectric dielectric, e.g. hydrogen. Subsequent processing then proceeds in a conventional manner, to complete the interconnect metallization.
There are several technical difficulties associated with this scheme. For example, the capacitor structure is close to the active devices. Contamination is a critical concern unless the defectivity level in the barrier layer is low enough to prevent diffusion and safeguard the integrity of the active devices. The capping layer must be an insulator, and preferably should provide some protection to the capacitor structure during subsequent processing. Even with a capping layer, the capacitor may be subject to ion bombardment during subsequent processing, e.g. reactive ion etching during formation of the interconnect.
Moreover, the placement of the capacitors underneath interconnect metallization reduces the porosity of the interconnect routing, i.e. the interconnect must be routed around, rather than through, a relatively large area occupied by the capacitors. Thus the interconnect routing efficiency is restricted, which limits the packing density of the underlying devices.
Placing a ferroelectric capacitor below several layers of interconnects and thick dielectrics may cause stress, which may induce stress related fatigue of the ferroelectric material. Moreover, exposure to the diffused hydrogen commonly used in the subsequent metal deposition steps and sintering, i.e. to form interconnect materials, can chemically reduce a PZT film and cause premature fatigue.
Consequently, while ferroelectric capacitors show potential as compact, high capacitance capacitors for integrated circuits, many processing related problems in known structures and process schemes remain to be solved. On the other hand, large value capacitors formed with conventional dielectrics take up unacceptably large areas, which restrict device packing density and interconnect routing efficiency in advanced submicron technologies.